1. Technical Field
The embodiments described herein relate to semiconductor circuit technology and, more particularly, to a differential amplifier and an input circuit using the same.
2. Related Art
A conventional semiconductor memory device includes a signal transferring unit for receiving and transferring a signal and a signal processing unit for processing the signal transferred from the signal transferring unit according to a prescribed operation.
A conventional signal processing unit is also called a core circuit. A conventional core circuit integrates different kinds of elements. In fact a conventional core circuit will includes as many elements as is possible within the limits of the associated design technology and the processing capacity of the semiconductor memory device.
For example, a conventional core unit includes an input circuit for transferring an input signal to the core unit, and an output circuit for outputting data from the core unit.
The input circuit receives various signals transferred from the outside, namely, an address signal, a clock signal, and data signal and transfers them to the core circuit positioned inside the semiconductor memory device. The output circuit outputs the data, which correspond to the received address. Therefore, the input circuit, which receives the data and address signals, should perform an accurate buffering operation to ensure reliable operation.
A conventional input circuit includes a differential amplifier having a MOS transistor (hereinafter, a transistor). The operational characteristic of the transistor can be changed by a PVT (process, voltage, temperature) fluctuation. Also, when the input circuit is included in a mobile device, a termination operation is not performed in order to minimize operating current and conserve power; however, forgoing the termination operation can result in a voltage change. This is because the termination operation controls the voltage levels of input signals ‘IN’ and ‘VREF’ to be within a prescribed range, to cope with the fluctuation of external high and low voltages (VDD) and (VSS), ‘.
As shown in FIG. 1, when the termination operation is performed, the input signals ‘IN’ and ‘VREF’ have a voltage swing that is bounded by the external high voltage (VDD). The input signal ‘IN’ can be a clock signal and the input signal ‘VREF’ can be out of phase with the clock signal.
Meanwhile, as shown in FIG. 1, when the terminal operation is not performed, the input signals ‘IN’ and ‘VREF’ swing in an abnormal voltage range that can be bounded by an external low voltage (VSS). In such situations, the middle voltage (Vmp) of the input signals ‘IN’ and ‘VREF’ is less than ½(VDD) because of the termination operation is not performed. AS a result, the gate-source voltage (Vgs) of a transistor that receives the input signals ‘IN’ and ‘VREF’ can be low as compared with the threshold voltage (Vth) of the transistor. When the gate-source voltage (Vgs) is lower than the threshold voltage (Vth), the transistor cannot operate, and thus the input circuit operates abnormally or cannot operate at all.
Although the duty ratio of the input signals ‘IN’ and ‘VREF’ is constant, if the input circuit operates abnormally or cannot operate at all, then the duty ratio of an output signal of the input circuit can be distorted. As shown in FIG. 2, when the middle voltage (Vmp) is less than 50 percent of the external voltage (VDD), the duty ratio of the output signal of the input circuit is rapidly distorted to be less than 50 percent. If the duty ratio is distorted, the margin of a setup/hold time is reduced. Eventually, the semiconductor memory device will produce an output error.